1. Field of the Invention
The present invention relates to an operation method for a non-volatile memory structure; in particular, to an operation method for a nitride-based flash memory and a method for reducing coupling interference of a nitride-based flash memory.
2. Description of Related Art
In general, the non-volatile memory cell is comprised of a stacked gate, made of doped polysilicon and consisting of a floating gate and a control gate. A dielectric layer is disposed between the floating gate and the control gate, while a tunnel oxide layer is located between the floating gate and the substrate. The floating gate is disposed between the substrate and the control gate and in a “floated” state (i.e. not being electrically connected with any circuit). The control gate is electrically connected with the word line. The floating gate is used to store charges, while the control gate is used to control a data writing/reading operation. The memory cell having the floating gate structure can be used as one bit/cell, single level cell (SLC) or multi-level cell (MLC). As the floating gate based memory cell is continuingly scaled down and the distance between each two word-lines becomes too close, the coupling interference issues occur and result in a threshold voltage shift (Vt shift), which is one major problem faced in the industry.
In addition to the aforementioned floating-gate-based memory cell, a nitride-based memory cell that uses silicon nitride to be a charge trapping layer as a replacement for the polysilicon floating gate has become another mainstream non-volatile memory cell. Despite that the nitride-based memory cell can store 2 or more bits per cell and its fabrication is compatible with MOS technology, the nitride-based memory cell was formerly assumed free of coupling interference issues.
However, it is found that the nitride-based memory structure has similar coupling interference issues. Referring to FIG. 1, FIG. 1 is a diagram illustrating a relationship between currents and voltages measured when performing a reading operation on two different sized memory cells and applying a negative bias voltage to word lines at two sides of the memory cell. In FIG. 1, -▪- represents the measurement results of the currents and the voltages according to a smaller sized memory cell D2; -●-represents the measurement results of the currents and the voltages according to a bigger sized memory cell D1; X axis represents a gate voltage (VG); and Y axis represents a read current. As shown in FIG. 1, after the size of the memory cell is miniaturized, which means a spacing between each two adjacent word lines is shorten, the read current is more prone to be impacted by the bias change of adjacent word lines.
Referring to FIG. 2A and FIG. 2B, FIG. 2A and FIG. 2B are a top view of a word line layout and a diagram illustrating a relationship between bit counts and Vt shift values for different word lines respectively. FIG. 2A illustrates 8 word lines WL0˜WL7 arranged in parallel, wherein the critical dimension of the word lines is 75 nm. In FIG. 2B, -∘- represents a voltage distribution curve as a whole, and -●--▴- -▾- and -♦- are the voltage distribution curves for the word lines WL1, WL3, WL5 and WL7 respectively. As shown in FIG. 2A and FIG. 2B, when the bits of the word lines WL0, WL2, WL4 and WL6 are programmed to reach a “0” state, the Vt shift values of the adjacent word lines WL1, WL3, WL5 and WL7 increase.
From the experiment results, when scaling down the size of the memory cell, if the distance between each two adjacent word lines is too close, the coupling interference issue of the nitride-based memory cell arises. Moreover, it is known from FIG. 2A and FIG. 2B that the Vt shift values of the word lines, WL1, WL3 and WL5 which have interference from two sides are bigger, while the Vt shift value of the word line WL7 which has interference from one side is smaller.
FIG. 3 is a Vt distribution diagram for the nitride-based memory cell without consideration of the coupling interference issue (shown in dotted line) and in consideration of the coupling interference issue respectively. As shown in FIG. 3, the coupling interference makes the Vt where the data storage state is “1” shift from the curve 310 to the curve 312, and makes the Vt where the data storage state is “0” shift from the curve 320 to the curve 322. Hence, the operation window W becomes relatively narrower than the operation window W0.
As the coupling interference issue existing in the nitride-based memory makes the operation window narrower, it is desirable to reduce or mitigate the coupling interference issue for the development of better quality or smaller sized non-volatile memory.